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LT3844 High Voltage, Current Mode Switching Regulator Controller with Programmable Operating Frequency DESCRIPTIO
The LT(R)3844 is a DC/DC controller used for medium power, low part count, high efficiency supplies. It offers a wide 4V-60V input range (7.5V minimum startup voltage) and can implement step-down, step-up, inverting and SEPIC topologies. The LT3844 includes Burst Mode operation, which reduces quiescent current below 120A and maintains high efficiency at light loads. An internal high voltage bias regulator allows for simple biasing. Additional features include current mode control for fast line and load transient response; programmable fixed operating frequency that can be synchronized to an external clock for noise sensitive applications; a gate driver capable of driving large N-channel MOSFETs; a precision undervoltage lockout function; 10A shutdown current; short-circuit protection and a programmable soft-start function. The LT3844 is available in a 16-lead thermally enhanced TSSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5731694, 6498466, 6611131.
FEATURES

High Voltage Operation: Up to 60V Output Voltages up to 36V (Step-Down) Programmable Constant Frequency: 100kHz to 500kHz Synchronizable up to 600kHz Burst Mode(R) Operation: 120A Supply Current 10A Shutdown Supply Current 1.3% Reference Accuracy Drives N-Channel MOSFET Programmable Soft-Start Programmable Undervoltage Lockout Internal High Voltage Regulator for Gate Drive Thermal Shutdown Current Limit Unaffected by Duty Cycle 16-Pin Thermally Enhanced TSSOP Package
APPLICATIO S

Industrial Power Distribution 12V and 42V Automotive and Heavy Equipment High Voltage Single Board Systems Distributed Power Systems Avionics Telecom Power
TYPICAL APPLICATIO
VIN 36V TO 60V
High Voltage Step-Down Regulator 48V to 12V, 50W
90
68F
22F
1 MEG VIN 1000pF 82.5k
SHDN CSS BURST_EN
0.22F BOOST
88 6 EFFICIENCY 5 4 3 2 1 VIN = 48V 1 LOAD CURRENT (A) 0 10
10 SW VCC LT3844
VFB
EFFICIENCY (%)
TG
Si7850DP
10H 1F PDS5100H
0.02
PGND SENSE+ SENSE- SGND
10k
VC
VOUT 12V 50W 68F 33F
130k
14.7k
680p
120pF
SYNC fSET
3844 TA01
R7 49.9k
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Efficiency and Power Loss vs Load Current
7
86 84 82 80 78 76 0.1
POWER LOSS (W)
LOSS
3844 TA01b
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LT3844
ABSOLUTE
(Note 1)
AXI U RATI GS
PI CO FIGURATIO
TOP VIEW VIN SHDN CSS BURST_EN VFB VC SYNC fSET 1 2 3 4 5 6 7 8 17
Input Supply Voltage (VIN)......................... 65V to -0.3V Boosted Supply Voltage (BOOST) .............. 80V to -0.3V Switch Voltage (SW) (Note 8) ...................... 65V to -1V Differential Boost Voltage (BOOST to SW) ..................................... 24V to -0.3V Bias Supply Voltage (VCC) ......................... 24V to -0.3V SENSE+ and SENSE- Voltages ................... 40V to -0.3V Differential Sense Voltage (SENSE+ to SENSE-) .................................. 1V to -1V BURST_EN Voltage .................................... 24V to -0.3V SYNC, VC, VFB, CSS, and SHDN Voltages ..... 5V to -0.3V SHDN Pin Currents ................................................. 1mA Operating Junction Temperature Range (Note 2) LT3844E (Note 3) ..............................-40C to 125C LT3844I .............................................-40C to 125C Storage Temperature .............................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 40C/W, JC = 10C/W EXPOSED PAD IS SGND (PIN 17) MUST BE SOLDERED TO PCB
ORDER I FOR ATIO
LEAD FREE FINISH LT3844EFE#PBF LT3844IFE#PBF
TAPE AND REEL LT3844EFE#TRPBF LT3844IFE#TRPBF
PART MARKING 3844EFE 3844IFE
PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, RSET = 49.9k, SENSE - = SENSE + = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
PARAMETER VIN Operating Voltage Range (Note 4) VIN Minimum Start Voltage VIN UVLO Threshold (Falling) VIN UVLO Threshold Hysteresis VIN Supply Current VIN Burst Mode Current VIN Shutdown Current BOOST Operating Voltage Range BOOST Operating Voltage Range (Note 5) BOOST UVLO Threshold (Rising) BOOST UVLO Threshold Hysteresis BOOST Supply Current (Note 6) BOOST Burst Mode Current BOOST Shutdown Current VCC > 9V VBURST_EN = 0V, VFB = 1.35V VSHDN = 0V VBOOST - VSW VBOOST - VSW VBOOST - VSW VBURST_EN = 0V VSHDN = 0V CONDITIONS

ELECTRICAL CHARACTERISTICS
MIN 4 3.6

2
U
16 BOOST 15 TG 14 SW 13 VCC 12 PGND 11 SENSE+ 10 SENSE - 9 SGND
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WW
W
W
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TEMPERATURE RANGE -40C to 125C -40C to 125C
TYP
MAX 60 7.5 4
UNITS V V V mV A A A V V V mV mA A A
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3.8 670 20 20 10
15 75 20
5 400 1.4 0.1 0.1
LT3844
ELECTRICAL CHARACTERISTICS
PARAMETER VCC Operating Voltage Range (Note 5) VCC Output Voltage VCC UVLO Threshold (Rising) VCC UVLO Threshold Hysteresis VCC Supply Current (Note 6) VCC Burst Mode Current VCC Shutdown Current VCC Current Limit Error Amp Reference Voltage VFB Pin Input Current SHDN Enable Threshold (Rising) SHDN Threshold Hysteresis Sense Pins Common Mode Range Current Limit Sense Voltage Input Current (ISENSE+ + ISENSE-) Operating Frequency
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, RSET = 49.9k, SENSE - = SENSE + = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
CONDITIONS Over Full Line and Load Range

MIN
TYP 8 6.25 500 1.7 95 20 -120 1.231 25
MAX 20 8.3
UNITS V V V mV mA A A mA V V nA V mV V mV A A A
2.1
VBURST_EN = 0V VSHDN = 0V
-40 1.224 1.215 1.3 0 90
Measured at VFB Pin
1.238 1.245 1.4 36 115
VFB = 1.231V

1.35 120 100 350 -25 -170
VSENSE+ - VSENSE- VSENSE(CM) = 0V VSENSE(CM) = 2V VSENSE(CM) > 4V
290 270 500 100
300
310 330 100 600
kHz kHz kHz kHz kHz k V A S dB A V V ns
Minimum Programmable Frequency Maximum Programmable Frequency External Sync Frequency Range SYNC Input Resistance SYNC Voltage Threshold Soft-Start Capacitor Control Current Error Amp Transconductance Error Amp DC Voltage Gain Error Amp Sink/Source Current TG Drive On Voltage (Note 7) TG Drive Off Voltage TG Drive Rise/Fall Time Minimum TG Off Time Minimum TG On Time Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3844 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The LT3844E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3844I is guaranteed CLOAD = 2200pF CLOAD = 2200pF 10% to 90% or 90% to 10%, CLOAD = 2200pF

40 1.4 2 270 340 62 30 9.8 0.1 40

2 410
350 250
500 350
ns ns
over the full -40C to 125C operating junction temperature range. Note 4: VIN voltages below the start-up threshold (7.5V) are only supported when the VCC is externally driven above 6.5V. Note 5: Operating range is dictated by MOSFET absolute maximum VGS. Note 6: Supply current specification does not include switch drive currents. Actual supply currents will be higher. Note 7: DC measurement of gate drive output "ON" voltage is typically 8.6V. Internal dynamic bootstrap operation yields typical gate "ON" voltages of 9.8V during standard switching operation. Standard operation gate "ON" voltage is not tested but guaranteed by design. Note 8: The -1V absolute maximum on the SW pin is a transient condition. It is guaranteed by design and not subject to test.
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LT3844 TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold (Rising) vs Temperature
1.38 1.26
SHUTDOWN THRESHOLD, FALLING (V)
SHUTDOWN THRESHOLD, RISING (V)
1.37 1.36 1.35 1.34 1.33 1.32 -50 -25
1.23 1.22 1.21 1.20 -50 -25
VCC (V)
0 50 25 75 TEMPERATURE (C)
VCC vs ICC(LOAD)
8.05 TA = 25C 9 8 8.00 7
ICC CURRENT LIMIT (mA)
VCC (V)
7.95
VCC (V)
7.90 4 7.85 3
0
5
10
15 20 25 ICC(LOAD) (mA)
30
VCC UVLO Threshold (Rising) vs Temperature
6.5 25
ERROR AMP TRANSCONDUCTANCE (S)
VCC UVLO THRESHOLD, RISING (V)
6.4
ICC (A)
6.3
6.2
6.1
6.0 -50 -25
0 25 50 75 TEMPERATURE (C)
4
UW
100
3844 G01
Shutdown Threshold (Falling) vs Temperature
8.2 8.1 8.0 1.24 7.9 7.8 7.7 7.6
VCC vs Temperature
ICC = 20mA
1.25
125
0 50 25 75 TEMPERATURE (C)
100
125
7.5 -50 -25
0 25 50 75 TEMPERATURE (C)
100
125
3844 G02
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VCC vs VIN
200 ICC = 20mA TA = 25C 175 150 125 100 75
ICC Current Limit vs Temperature
6 5
35
40
4
5
6
7
8 VIN (V)
9
10
11
12
50 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
3844 G04
3844 G05
3844 G06
ICC vs VCC (SHDN = 0V)
TA = 25C 350 345 340 335 330 325
Error Amp Transconductance vs Temperature
20
15
10
5
100
125
0
0
2
4
6
8
10 12 14 16 18 20 VCC (V)
3844 G08
320 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3844 G07
3844 G09
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LT3844 TYPICAL PERFOR A CE CHARACTERISTICS
I(SENSE+ + SENSE-) vs VSENSE (CM)
400 TA = 25C
OPERATING FREQUENCY (kHz)
I(SENSE+ + SENSE -) (A)
304 302 300 298 296 294 292
ERROR AMP REFERENCE (V)
300 200 100 0
-100 -200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE (CM) (V)
3844 G10
Maximum Current Sense Threshold vs Temperature
106
CURRENT SENSE THRESHOLD (mV)
104 102 100 98 96 94 -50 -25
VIN UVLO THRESHOLD, RISING (V)
4.52 4.50 4.48 4.46 4.44 4.42 4.40 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
VIN UVLO THRESHOLD, FALLING (V)
PI FU CTIO S
VIN (Pin 1): The VIN pin is the main supply pin and should be decoupled to SGND with a low ESR capacitor located close to the pin. SHDN (Pin 2): The SHDN pin has a precision IC enable threshold of 1.35V (rising) with 120mV of hysteresis. It is used to implement an undervoltage lockout (UVLO) circuit. See Application Information section for implementing a UVLO function. When the SHDN pin is pulled below a transistor VBE (0.7V), a low current shutdown mode is entered, all internal circuitry is disabled and the VIN supply current is reduced to approximately 9A. Typical pin input bias current is <10A and the pin is internally clamped to 6V. CSS (Pin 3): The soft-start pin is used to program the supply soft-start function. Use the following formula to calculate CSS for a given output voltage slew rate: CSS = 2A(tSS/1.231V) The pin should be left unconnected when not using the soft-start function.
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UW
3844 G16
Operating Frequency vs Temperature
308 306 1.234 1.233 1.232 1.231 1.230 1.229 1.228
Error Amp Reference vs Temperature
290 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1.227 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3844 G17
3844 G12
VIN UVLO Threshold (Rising) vs Temperature
4.54 3.86
VIN UVLO Threshold (Falling) vs Temperature
3.84
3.82
3.80
3.78
3.76 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3844 G14
3844 G15
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LT3844
PI FU CTIO S
BURST_EN (Pin 4): The BURST_EN pin is used to enable or disable Burst Mode operation. Connect the BURST_EN pin to ground to enable the burst mode function. Connect the pin to VFB or VCC to disable the burst mode function. VFB (Pin 5): The output voltage feedback pin, VFB, is externally connected to the supply output voltage via a resistive divider. The VFB pin is internally connected to the inverting input of the error amplifier. In regulation, VFB is 1.231V. VC (Pin 6): The VC pin is the output of the error amplifier whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifier is typically configured as an integrator circuit by connecting an RC network from the VC pin to SGND. This circuit creates the dominant pole for the converter regulation control loop. Specific integrator characteristics can be configured to optimize transient response. When Burst Mode operation is enabled (see Pin 4 description), an internal low impedance clamp on the VC pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low impedance source. If the VC pin must be externally manipulated, do so through a 1k series resistance. SYNC (Pin 7): The Sync pin provides an external clock input for synchronization of the internal oscillator. RSET is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. If unused the Sync pin is connected to SGND. For more information see "Oscillator Sync" in the Application Information section of this datasheet. fSET (Pin 8): The fSET pin programs the oscillator frequency with an external resistor, RSET. The resistor is required even when supplying external sync clock signal. See the Applications Information section for resistor value selection details. SGND (Pin 9, 17): The SGND pin is the low noise ground reference. It should be connected to the -VOUT side of the output capacitors. Careful layout of the PCB is necessary to keep high currents away from this SGND connection. See the Application Information section for helpful hints on PCB layout of grounds. SENSE - (Pin 10): The SENSE- pin is the negative input for the current sense amplifier and is connected to the VOUT side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. SENSE+ (Pin 11): The SENSE+ pin is the positive input for the current sense amplifier and is connected to the inductor side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. PGND (Pin 12): The PGND pin is the high-current ground reference for internal low side switch and the VCC regulator circuit. Connect the pin directly to the negative terminal of the VCC decoupling capacitor. See the Application Information section for helpful hints on PCB layout of grounds. VCC (Pin 13): The VCC pin is the internal bias supply decoupling node. Use a low ESR 1F or greater ceramic capacitor to decouple this node to PGND. Most internal IC functions are powered from this bias supply. An external diode connected from VCC to the BOOST pin charges the bootstrapped capacitor during the off-time of the main power switch. Back driving the VCC pin from an external DC voltage source, such as the VOUT output of the regulator supply, increases overall efficiency and reduces power dissipation in the IC. In shutdown mode this pin sinks 20A until the pin voltage is discharged to 0V. SW (Pin 14): In step-down applications the SW pin is connected to the cathode of an external clamping Schottky diode, the drain of the power MOSFET and the inductor. The SW node voltage swing is from VIN during the on-time of the power MOSFET, to a Schottky voltage drop below ground during the off-time of the power MOSFET. In startup and in operating modes where there is insufficient inductor current to freewheel the Schottky diode, an internal switch is turned on to pull the SW pin to ground so that the BOOST pin capacitor can be charged. Give careful consideration in choosing the Schottky diode to limit the negative voltage swing on the SW pin. TG (Pin 15): The TG pin is the bootstrapped gate drive for the top N-Channel MOSFET. Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02" width, PCB trace to minimize inductance.
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LT3844
PI FU CTIO S
BOOST (Pin 16): The BOOST pin is the supply for the bootstrapped gate drive and is externally connected to a low ESR ceramic boost capacitor referenced to SW pin. The recommended value of the BOOST capacitor,CBOOST, is 50 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1F is adequate. The maximum voltage that this pin sees is VIN + VCC, ground referred. Exposed Pad (SGND) (Pin 17): The exposed leadframe is internally connected to the SGND pin. Solder the exposed pad to the PCB ground for electrical contact and optimal thermal performance.
FU CTIO AL DIAGRA
VIN UVLO (<4V) VIN VIN CIN 1
8V REGULATOR
RA
VREF
-
SHDN 2 RB
+
BURST_EN 4 VFB 5 R1 R2 100mV VC 6 CC2 CC1
-
gm + ERROR AMP
0.5V Q S
~1V CSS CLAMPED TO VFB + VBE
VREF + 200mV 3 CSS 2A
FAULT CONDITION: V UVLO 50A VIN UVLO CC VSHDN UVLO
+
+
-
RC
+ -
BURST MODE OPERATION
-
+
+
-
-
W
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VCC UVLO (<6V) 3.8V REGULATOR INTERNAL SUPPLY RAIL
BST UVLO
BOOSTED SWITCH DRIVER
BOOST 16 CBOOST
FEEDBACK REFERENCE 1.231V
DRIVE CONTROL
DRIVER
TG 15
M1
NOL SWITCH LOGIC
SW 14 VCC 13 CVCC D2 D1
L1
RSENSE VOUT COUT
D3 (OPTIONAL)
DRIVE CONTROL
PGND 12
SYNC 7 OSCILLATOR 8 RSET R CURRENT SENSE COMPARATOR SLOPE COMP GENERATOR fSET
SOFT-START BURST DISABLE
-
+
9
SGND
SENSE+ 11 SENSE- 10
3844 FD
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LT3844
OPERATIO
The LT3844 is a PWM controller with a constant frequency, current mode control architecture. It is designed for low to medium power, switching regulator applications. Its high operating voltage capability allows it to stepup or down input voltages up to 60V without the need for a transformer. The LT3844 is used in nonsynchronous applications, meaning that a freewheeling rectifier diode (D1 of Function Diagram) is used instead of a bottom side MOSFET. For circuit operation, please refer to the Functional Diagram of the IC and Typical Application on the front page of the data sheet. The LT3800 is a similar part that uses synchronous rectification, replacing the diode with a MOSFET in a step-down application. Main Control Loop During normal operation, the external N-channel MOSFET switch is turned on at the beginning of each cycle. The switch stays on until the current in the inductor exceeds a current threshold set by the DC control voltage, VC, which is the output of the voltage control loop. The voltage control loop monitors the output voltage, via the VFB pin voltage, and compares it to an internal 1.231V reference. It increases the current threshold when the VFB voltage is below the reference voltage and decreases the current threshold when the VFB voltage is above the reference voltage. For instance, when an increase in the load current occurs, the output voltage drops causing the VFB voltage to drop relative to the 1.231V reference. The voltage control loop senses the drop and increases the current threshold. The peak inductor current is increased until the average inductor current equals the new load current and the output voltage returns to regulation. Current Limit/Short-Circuit The inductor current is measured with a series sense resistor (see the Typical Application on the front page). When the voltage across the sense resistor reaches the maximum current sense threshold, typically 100mV, the TG MOSFET driver is disabled for the remainder of that cycle. If the maximum current sense threshold is still exceeded at the beginning of the next cycle, the entire cycle is skipped. Cycle skipping keeps the inductor currents to a reasonable value during a short-circuit, particularly when VIN is high. Setting the sense resistor value is discussed in the "Application Information" section.
8
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(Refer to Functional Diagram)
VCC/Boosted Supply An internal VCC regulator provides VIN derived gate-drive power for start-up under all operating conditions with MOSFET gate charge loads up to 90nC. The regulator can operate continuously in applications with VIN voltages up to 60V, provided the power dissipation of the regulator does not exceed 250mW. The power dissipation is calculated as follows: Pd(REG) = (VIN - 8V) * fSW * QG where QG is the MOSFET gate charge. In applications where these conditions are exceeded, VCC must be derived from an external source after start-up. Maximum continuous regulator power dissipation may be exceeded for short duration VIN transients. For higher converter efficiency and less power dissipation in the IC, VCC can also be supplied from an external supply such as the converter output. When an external supply back drives the internal VCC regulator through an external diode and the VCC voltage is pulled to a diode above its regulation voltage, the internal regulator is disabled and goes into a low current mode. VCC is the bias supply for most of the internal IC functions and is also used to charge the bootstrapped capacitor (CBOOST) via an external diode. The external MOSFET switch is biased from the bootstrapped capacitor. While the external MOSFET switch is off, an internal BJT switch, whose collector is connected to the SW pin and emitter is connected to the PGND pin, is turned on to pull the SW node to PGND and recharge the bootstrap capacitor. The switch stays on until either the start of the next cycle or until the bootstrapped capacitor is fully charged. MOSFET Driver The LT3844 contains a high speed boosted driver to turn on and off an external N-channel MOSFET switch. The MOSFET driver derives its power from the boost capacitor which is referenced to the SW pin and the source of the MOSFET. The driver provides a large pulse of current to turn on the MOSFET fast to minimize transition times. Multiple MOSFETs can be paralleled for higher current operation.
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LT3844
OPERATIO U
(Refer to Functional Diagram)
To eliminate the possibility of shoot through between the MOSFET and the internal SW pull-down switch, an adaptive nonoverlap circuit ensures that the internal pull-down switch does not turn on until the gate of the MOSFET is below its turn on threshold. Low Current Operation (Burst Mode Operation) To increase low current load efficiency, the LT3844 is capable of operating in Linear Technology's proprietary Burst Mode operation where the external MOSFET operates intermittently based on load current demand. The Burst Mode function is disabled by connecting the BURST_EN pin to VCC or VFB and enabled by connecting the pin to SGND. When the required switch current, sensed via the VC pin voltage, is below 15% of maximum, Burst Mode operation is employed and that level of sense current is latched onto the IC control path. If the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. This overdrive condition is sensed internally and forces the voltage on the VC pin to continue to drop. When the voltage on VC drops 150mV below the 15% load level, switching is disabled, and the LT3844 shuts down most of its internal circuitry, reducing total quiescent current to 120A. When the converter output begins to fall, the VC pin voltage begins to climb. When the voltage on the VC pin climbs back to the 15% load level, the IC returns to normal operation and switching resumes. An internal clamp on the VC pin is set at 100mV below the output disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during Burst Mode operation. During Burst Mode operation, the VIN pin current is 20A and the VCC current is reduced to 100A. If no external drive is provided for VCC, all VCC bias currents originate from the VIN pin, giving a total VIN current of 120A. Burst current can be reduced further when VCC is driven using an output derived source, as the VCC component of VIN current is then reduced by the converter duty cycle ratio.
Start-Up The following section describes the start-up of the supply and operation down to 4V once the step-down supply is up and running. For the protection of the LT3844 and the switching supply, there are internal undervoltage lockout (UVLO) circuits with hysteresis on VIN, VCC and VBOOST, as shown in the Electrical Characteristics table. Start-up and continuous operation require that all three of these undervoltage lockout conditions be satisfied because the TG MOSFET driver is disabled during any UVLO fault condition. In startup, for most applications, VCC is powered from VIN through the high voltage linear regulator of the LT3844. This requires VIN to be high enough to drive the VCC voltage above its undervoltage lockout threshold. VCC, in turn, has to be high enough to charge the BOOST capacitor through an external diode so that the BOOST voltage is above its undervoltage lockout threshold. There is an NPN switch that pulls the SW node to ground each cycle during the TG power MOSFET off-time, ensuring the BOOST capacitor is kept fully charged. Once the supply is up and running, the output voltage of the supply can backdrive VCC through an external diode. Internal circuitry disables the high voltage regulator to conserve VIN supply current. Output voltages that are too low or too high to backdrive VCC require additional circuitry such as a voltage doubler or linear regulator. Once VCC is backdriven from a supply other than VIN, VIN can be reduced to 4V with normal operation maintained. Soft-Start The soft-start function controls the slew rate of the power supply output voltage during start-up. A controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the VIN supply, and facilitates supply sequencing. A capacitor, CSS, connected from the CSS pin to SGND, programs the slew rate. The capacitor is charged from an internal 2A current source producing a ramped voltage. The capacitor voltage overrides the internal reference to the error amplifier. If the VFB pin voltage
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LT3844
OPERATIO
exceeds the CSS pin voltage then the current threshold set by the DC control voltage, VC, is decreased and the inductor current is lowered. This in turn decreases the output voltage slew rate allowing the CSS pin voltage ramp to catch up to the VFB pin voltage. An internal 100mV offset is added to the VFB pin voltage relative to the to CSS pin voltage so that at start-up the soft-start circuit will discharge the VC pin voltage below the DC control voltage equivalent to zero inductor current. This will reduce the input supply inrush current. The soft-start circuit is disabled once the CSS pin voltage has been charged to 200mV above the internal reference of 1.231V. During a VIN UVLO, VCC UVLO or SHDN UVLO event, the CSS pin voltage is discharged with a 50A current source. In normal operation the CSS pin voltage is clamped to a diode above the VFB pin voltage. Therefore, the value of the CSS capacitor is relevant in how long of a fault event will retrigger a soft-start. In other words, if any of the above UVLO conditions occur, the CSS pin voltage will be discharged with a 50A current source. There is a diode worth of voltage headroom to ride through the fault before the CSS pin voltage enters its active region and the soft-start function is enabled. Also, since the CSS pin voltage is clamped to a diode above the VFB pin voltage, during a short circuit the CSS pin voltage is pulled low because the VFB pin voltage is low. Once the short has been removed the VFB pin voltage starts to recover. The soft-start circuit takes control of the output voltage slew rate once the VFB pin voltage has exceeded the slowly ramping CSS pin voltage, reducing the output voltage overshoot during a short circuit recovery.
APPLICATIO S I FOR ATIO
The basic LT3844 step-down (buck) application, shown in the Typical Application on the front page, converts a larger positive input voltage to a lower positive or negative output voltage. This Application Information section assists selection of external components for the requirements of the power supply.
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(Refer to Functional Diagram)
Slope/Antislope Compensation The IC incorporates slope compensation to eliminate potential subharmonic oscillations in the current control loop. The IC's slope compensation circuit imposes an artificial ramp on the sensed current to increase the rising slope as duty cycle increases. Typically, this additional ramp affects the sensed current value, thereby reducing the achievable current limit value by the same amount as the added ramp represents. As such, the current limit is typically reduced as the duty cycle increases. The LT3844, however, contains antislope compensation circuitry to eliminate the current limit reduction associated with slope compensation. As the slope compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold. The end result is that the current limit is not compromised so the LT3844 can provide full power regardless of required duty cycle. Shutdown The LT3844 includes a shutdown mode where all the internal IC functions are disabled and the VIN current is reduced to less than 10A. The shutdown pin can be used for undervoltage lockout with hysteresis, micropower shutdown or as a general purpose on/off control of the converter output. The shutdown function has two thresholds. The first threshold, a precision 1.23V threshold with 120mV of hysteresis, disables the converter from switching. The second threshold, approximately a 0.7V referenced to SGND, completely disables all internal circuitry and reduces the VIN current to less than 10A. See the Application Information section for more information.
RSENSE Selection The current sense resistor, RSENSE, monitors the inductor current of the supply (See Typical Application on front page). Its value is chosen based on the maximum required output load current. The LT3844 current sense amplifier has a maximum voltage threshold of, typically, 100mV.
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Therefore, the peak inductor current is 100mV/RSENSE. The maximum output load current, IOUT(MAX), is the peak inductor current minus half the peak-to-peak ripple current, IL. Allowing adequate margin for ripple current and external component tolerances, RSENSE can be calculated as follows: RSENSE = 70mV IOUT(MAX )
Typical values for RSENSE are in the range of 0.005 to 0.05. Operating Frequency The choice of operating frequency and inductor value is a trade off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses and gate charge losses. However, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a larger inductor size and higher cost. If the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. For converters with high step-down VIN to VOUT ratios, another consideration is the minimum on-time of the LT3844 (see the Minimum On-time Considerations section). A final consideration for operating frequency is that in noise200 180 160 140
RSET (k)
120 100 80 60 40 20 0 100 200 300 400 FREQUENCY (kHz) 500 600
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Figure 1. Timing Resistor (RSET) Value
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sensitive communications systems, it is often desirable to keep the switching noise out of a sensitive frequency band. The LT3844 uses a constant frequency architecture that can be programmed over a 100kHz to 500kHz range with a single resistor from the fSET pin to ground, as shown in Figure 1. The nominal voltage on the fSET pin is 1V and the current that flows from this pin is used to charge an internal oscillator capacitor. The value of RSET for a given operating frequency can be chosen from Figure 4 or from the following equation:
RSET (k) = 8 . 4 * 104 * fSW(- 1 . 31)
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The following table lists typical resistor values for common operating frequencies:
Recommended 1% Standard Values RSET 191k 118k 80.6k 63.4k 49.9k 40.2k 33.2k 27.4k 23.2k fSW 100kHz 150kHz 200kHz 250kHz 300kHz 350kHz 400kHz 450kHz 500kHz
Step-Down Converter: Inductor Selection The critical parameters for selection of an inductor are minimum inductance value, volt-second product, saturation current and/or RMS current. For a given I, The minimum inductance value is calculated as follows:
L VOUT * VIN(MAX ) - VOUT fSW * VIN(MAX ) * IL
fSW is the switch frequency.
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The typical range of values for IL is (0.2 * IOUT(MAX)) to (0.5 * IOUT(MAX)), where IOUT(MAX) is the maximum load current of the supply. Using IL = 0.3 * IOUT(MAX) yields a good design compromise between inductor performance versus inductor size and cost. A value of IL = 0.3 * IOUT(MAX) produces a 15% of IOUT(MAX) ripple current around the DC output current of the supply. Lower values of IL require larger and more costly magnetics. Higher values of IL will increase the peak currents, requiring more filtering on the input and output of the supply. If IL is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. To satisfy slope compensation requirements the minimum inductance is calculated as follows:
L > VOUT *
2DCMAX - 1 RSENSE * 8.33 * DCMAX fSW
Some magnetics vendors specify a volt-second product in their datasheet. If they do not, consult the magnetics vendor to make sure the specification is not being exceeded by your design. The volt-second product is calculated as follows: Volt-second (sec) =
(VIN(MAX) - VOUT )* VOUT VIN(MAX) * fSW
The magnetics vendors specify either the saturation current, the RMS current or both. When selecting an inductor based on inductor saturation current, use the peak current through the inductor, IOUT(MAX) + IL/2. The inductor saturation current specification is the current at which the inductance, measured at zero current, decreases by a specified amount, typically 30%. When selecting an inductor based on RMS current rating, use the average current through the inductor, IOUT(MAX). The RMS current specification is the RMS current at which the part has a specific temperature rise, typically 40C, above 25C ambient. After calculating the minimum inductance value, the voltsecond product, the saturation current and the RMS current for your design, select an off-the-shelf inductor. Contact the Application group at Linear Technology for further support.
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For more detailed information on selecting an inductor, please see the "Inductor Selection" section of Linear Technology Application Note 44. Step-Down Converter: MOSFET Selection The selection criteria of the external N-channel standard level power MOSFET include on resistance(RDS(ON)), reverse transfer capacitance (CRSS), maximum drain source voltage (VDSS), total gate charge (QG) and maximum continuous drain current. For maximum efficiency, minimize RDS(ON) and CRSS. Low RDS(ON) minimizes conduction losses while low CRSS minimizes transition losses. The problem is that RDS(ON) is inversely related to CRSS. Balancing the transition losses with the conduction losses is a good idea in sizing the MOSFET. Select the MOSFET to balance the two losses. Calculate the maximum conduction losses of the MOSFET:
V PCOND = (IOUT (MAX) )2 OUT (RDS(ON) ) VIN
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Note that RDS(ON) has a large positive temperature dependence. The MOSFET manufacturer's data sheet contains a curve, RDS(ON) vs Temperature. Calculate the maximum transition losses: PTRAN = (k)(VIN)2 (IOUT(MAX))(CRSS)(fSW) where k is a constant inversely related to the gate driver current, approximated by k = 2 for LT3844 applications. The total maximum power dissipation of the MOSFET is the sum of these two loss terms: PFET(TOTAL) = PCOND + PTRAN To achieve high supply efficiency, keep the PFET(TOTAL) to less than 3% of the total output power. Also, complete a thermal analysis to ensure that the MOSFET junction temperature is not exceeded. TJ = TA + PFET(TOTAL) * JA where JA is the package thermal resistance and TA is the ambient temperature. Keep the calculated TJ below the maximum specified junction temperature, typically 150C.
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Note that when VIN is high and fSW is high, the transition losses may dominate. A MOSFET with higher RDS(ON) and lower CRSS may provide higher efficiency. MOSFETs with higher voltage VDSS specification usually have higher RDS(ON) and lower CRSS. Choose the MOSFET VDSS specification to exceed the maximum voltage across the drain to the source of the MOSFET, which is VIN(MAX) plus any additional ringing on the switch node. Ringing on the switch node can be greatly reduced with good PCB layout and, if necessary, an RC snubber. The internal VCC regulator is capable of sourcing up to 40mA which limits the maximum total MOSFET gate charge, QG, to 40mA/fSW. The QG vs VGS specification is typically provided in the MOSFET data sheet. Use QG at VGS of 8V. If VCC is back driven from an external supply, the MOSFET drive current is not sourced from the internal regulator of the LT3844 and the QG of the MOSFET is not limited by the IC. However, note that the MOSFET drive current is supplied by the internal regulator when the external supply back driving VCC is not available such as during startup or short-circuit. The manufacturer's maximum continuous drain current specification should exceed the peak switch current, IOUT(MAX) + IL/2. During the supply startup, the gate drive levels are set by the VCC voltage regulator, which is approximately 8V. Once the supply is up and running, the VCC can be back driven by an auxiliary supply such as VOUT. It is important not to exceed the manufacturer's maximum VGS specification. A standard level threshold MOSFET typically has a VGS maximum of 20V. Step-Down Converter: Rectifier Selection The rectifier diode (D1 on the Functional Diagram) in a buck converter generates a current path for the inductor current when the main power switch is turned off. The rectifier is selected based upon the forward voltage, reverse voltage and maximum current. A Schottky diode is recommended. Its low forward voltage yields the lowest power loss and highest efficiency. The maximum reverse voltage that the diode will see is VIN(MAX).
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In continuous mode operation, the average diode current is calculated at maximum output load current and maximum VIN:
IDIODE(AVG) = IOUT (MAX) VIN(MAX) - VOUT VIN(MAX)
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To improve efficiency and to provide adequate margin for short-circuit operation, a diode rated at 1.5 to 2 times the maximum average diode current, IDIODE(AVG), is recommended. Step-Down Converter: Input Capacitor Selection A local input bypass capacitor is required for buck converters because the input current is pulsed with fast rise and fall times. The input capacitor selection criteria are based on the bulk capacitance and RMS current capability. The bulk capacitance will determine the supply input ripple voltage. The RMS current capability is used to keep from overheating the capacitor. The bulk capacitance is calculated based on maximum input ripple, VIN:
CIN(BULK) = IOUT (MAX) * VOUT VIN * fSW * VIN(MIN)
VIN is typically chosen at a level acceptable to the user. 100mV-200mV is a good starting point. Aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor's RMS current is: ICIN(RMS) = IOUT VOUT (VIN - VOUT ) (VIN )2
If applicable, calculate it at the worst case condition, VIN = 2VOUT. The RMS current rating of the capacitor is specified by the manufacturer and should exceed the calculated ICIN(RMS). Due to their low ESR (Equivalent Series Resistance), ceramic capacitors are a good choice for high voltage, high RMS current handling. Note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes it
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advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. The combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meeting the input capacitor requirements. The capacitor voltage rating must be rated greater than VIN(MAX). Multiple capacitors may also be paralleled to meet size or height requirements in the design. Locate the capacitor very close to the MOSFET switch and use short, wide PCB traces to minimize parasitic inductance. Step-Down Converter: Output Capacitor Selection The output capacitance, COUT, selection is based on the design's output voltage ripple, VOUT and transient load requirements. VOUT is a function of IL and the COUT ESR. It is calculated by:
1 VOUT = IL * ESR + (8 * fSW * C OUT )
The maximum ESR required to meet a VOUT design requirement can be calculated by:
(VOUT )(L)(fSW ) ESR(MAX) = V VOUT * 1 - OUT VIN(MAX)
Worst-case VOUT occurs at highest input voltage. Use paralleled multiple capacitors to meet the ESR requirements. Increasing the inductance is an option to lower the ESR requirements. For extremely low VOUT, an additional LC filter stage can be added to the output of the supply. Application Note 44 has some good tips on sizing an additional output filter.
L1 VOUT R2 VFB PIN R1
3844 F02
COUT SHDN PIN
Figure 2. Output Voltage Feedback Divider
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Output Voltage Programming A resistive divider sets the DC output voltage according to the following formula: V R2 = R1 OUT - 1 1.231V The external resistor divider is connected to the output of the converter as shown in Figure 2. Tolerance of the feedback resistors will add additional error to the output voltage. Example: VOUT = 12V; R1 = 10k 12V R2 = 10k - 1 = 87.48k - use 86.6k 1% 1.231V The VFB pin input bias current is typically 25nA, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. Bias current error at the output can be estimated as: VOUT(BIAS) = 25nA * R2 Supply UVLO and Shutdown The SHDN pin has a precision voltage threshold with hysteresis which can be used as an undervoltage lockout threshold (UVLO) for the power supply. Undervoltage lockout keeps the LT3844 in shutdown until the supply input voltage is above a certain voltage programmed by the user. The hysteresis voltage prevents noise from falsely tripping UVLO. Resistors are chosen by first selecting RB. Then VSUPPLY(ON) RA = RB * - 1 1.35V
VSUPPLY RA RB
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Figure 3. Undervoltage Lockout Circuit
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VSUPPLY(ON) is the input voltage at which the undervoltage lockout is disabled and the supply turns on. Example: Select RB = 49.9k, VSUPPLY(ON) = 14.5V (based on a 15V minimum input voltage)
14.5V RA = 49.9k * -1 1.35V
= 486.1k (499k resistor is selected) If low supply current in standby mode is required, select a higher value of RB. The supply turn off voltage is 9% below turn on. In the example the VSUPPLY(OFF) would be 13.2V. If additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the LT3844 regulator output. The shutdown function can be disabled by connecting the SHDN pin to the VIN through a large value pull-up resistor. This pin contains a low impedance clamp at 6V, so the SHDN pin will sink current from the pull-up resistor(RPU):
ISHDN=
VIN - 6V RPU
Because this arrangement will clamp the SHDN pin to the 6V, it will violate the 5V absolute maximum voltage rating of the pin. This is permitted, however, as long as the absolute maximum input current rating of 1mA is not exceeded. Input SHDN pin currents of <100A are recommended: a 1M or greater pull-up resistor is typically used for this configuration. Soft-Start The desired soft-start time (tSS) is programmed via the CSS capacitor as follows:
CSS =
2A * tSS 1 . 231V
The amount of time in which the power supply can withstand a VIN, VCC or VSHDN UVLO fault condition (tFAULT) before the CSS pin voltage enters its active region is approximated by the following formula:
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tFAULT = CSS * 0 . 65V 50A
Oscillator SYNC The oscillator can be synchronized to an external clock. Set the RSET resistor at least 10% below the desired sync frequency. It is recommended that the SYNC pin be driven with a square wave that has amplitude greater than 2V, pulse width greater than 1s and rise time less than 500ns. The rising edge of the sync wave form triggers the discharge of the internal oscillator capacitor. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. Express percent efficiency as: % Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are individual loss terms as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main contributors usually account for most of the losses in LT3844 circuits: 1. LT3844 VIN and VCC current loss 2. I2R conduction losses 3. MOSFET transition loss 4. Schottky diode conduction loss 1. The VIN and VCC currents are the sum of the quiescent currents of the LT3844 and the MOSFET drive currents. The quiescent currents are in the LT3844 Electrical Characteristics table. The MOSFET drive current is a result of charging the gate capacitance of the power MOSFET each cycle with a packet of charge, QG. QG is found in the MOSFET data sheet. The average charging current is calculated as QG * fSW. The power loss term due to these currents can be reduced by backdriving VCC with a lower voltage than VIN such as VOUT.
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2. I2R losses are calculated from the DC resistances of the MOSFET, the inductor, the sense resistor and the input and output capacitors. In continuous conduction mode the average output current flows through the inductor and RSENSE but is chopped between the MOSFET and the Schottky diode. The resistances of the MOSFET (RDS(ON)) and the RSENSE multiplied by the duty cycle can be summed with the resistances of the inductor and RSENSE to obtain the total series resistance of the circuit. The total conduction power loss is proportional to this resistance and usually accounts for between 2% to 5% loss in efficiency. 3. Transition losses of the MOSFET can be substantial with input voltages greater than 20V. See MOSFET Selection section. 4. The Schottky diode can be a major contributor of power loss especially at high input to output voltage ratios (low duty cycles) where the diode conducts for the majority of the switch period. Lower Vf reduces the losses. Note that oversizing the diode does not always help because as the diode heats up the Vf is reduced and the diode loss term is decreased. I2R losses and the Schottky diode loss dominate at high load currents. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss in efficiency. PCB Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation. These items are illustrated graphically in the layout diagram of Figure 3. 1. Keep the signal and power grounds separate. The signal ground consists of the LT3844 SGND pin, the exposed pad on the backside of the LT3844 IC and the (-) terminal of VOUT. The signal ground is the quiet ground and does not contain any high, fast currents. The power ground consists of the Schottky diode anode, the (-) terminal of the input capacitor and the ground return of the VCC capacitor.
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This ground has very fast high currents and is considered the noisy ground. The two grounds are connected to each other only at the (-) terminal of VOUT. 2. Use short wide traces in the loop formed by the MOSFET, the Schottky diode and the input capacitor to minimize high frequency noise and voltage stress from parasitic inductance. Surface mount components are preferred. 3. Connect the VFB pin directly to the feedback resistors independent of any other nodes, such as the SENSE- pin. Connect the feedback resistors between the (+) and (-) terminals of COUT. Locate the feedback resistors in close proximity to the LT3844 to keep the high impedance node, VFB, as short as possible. 4. Route the SENSE- and SENSE+ traces together and keep as short as possible. 5. Locate the VCC and BOOST capacitors in close proximity to the IC. These capacitors carry the MOSFET driver's high peak currents. Place the small signal components away from high frequency switching nodes (BOOST, SW and TG). In the layout shown in Figure 3, place all the small signal components on one side of the IC and all the power components on the other. This helps to keep the signal and power grounds separate. 6. A small decoupling capacitor (100pF) is sometimes useful for filtering high frequency noise on the feedback and sense nodes. If used, locate as close to the IC as possible. 7. The LT3844 packaging will efficiently remove heat from the IC through the exposed pad on the backside of the part. The exposed pad is soldered to a copper footprint on the PCB. Make this footprint as large as possible to improve the thermal resistance of the IC case to ambient air. This helps to keep the LT3844 at a lower temperature. 8. Make the trace connecting the gate of MOSFET M1 to the TG pin of the LT3844 short and wide.
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RA 1 VIN BOOST TG RB 2 3 CSS 4 5 6 R2 CC1 R1 CC2 RSET RC 7 8 9 LT3844 SHDN CSS 17 VCC PGND SENSE 13 12 CVCC SW 16 15 14
BURST_EN VFB VC SYNC fSET SGND
SENSE-
Figure 4. LT3844 Layout Diagram (See PCB Layout Checklist).
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VIN+ CBOOST CIN VIN- L1 RSENSE M1
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D2 COUT D3 D1 VOUT
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10
-
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Minimum On-Time Considerations (Buck Mode) Minimum on-time tON(MIN) is the smallest amount of time that the LT3844 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the amount of gate charge required turning on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:
tON = VOUT > tON(MIN) VIN * fSW
where tON(MIN) is typically 350ns worst case. If the duty cycle falls below what can be accommodated by the minimum on-time, the LT3844 will begin to skip cycles. The output will be regulated, but the ripple current and ripple voltage will increase. If lower frequency operation is acceptable, the on-time can be increased above tON(MIN) for the same step-down ratio. Boost Converter Design The LT3844 can be used to configure a boost converter to step-up voltages to as high as hundreds of volts. An example of a boost converter circuit schematic is shown in the Typical Applications section. The following sections are a guide to designing a boost converter: The maximum duty cycle of the main switch is:
DCMAX =
VOUT - VIN(MIN) VOUT
Boost Converter: Inductor Selection The critical parameters for selection of an inductor are minimum inductance value and saturation current. The minimum inductance value is calculated as follows:
LMIN = VIN(MIN) IL * fSW * DCMAX
fSW is the switch frequency.
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Similar to the buck converter, the typical range of values for IL is (0.2 * IL(MAX)) to (0.5 * IL(MAX)), where I L(MAX) is the maximum average inductor current. IL(MAX ) = IOUT(MAX ) * VOUT VIN(MIN) Using IL = 0.3 * I L(MAX) yields a good design compromise between inductor performance versus inductor size and cost. The inductor must not saturate at the peak operating current, IL(MAX) + IL/2. The inductor saturation current specification is the current at which the inductance, measured at zero current, decreases by a specified amount, typically 30%. One drawback of boost regulators is that they cannot be current limited for output shorts because the current steering diode makes a direct connection between input and output. Therefore, the inductor current during an output short circuit is only limited by the available current of the input supply. After calculating the minimum inductance value and the saturation current for your design, select an off-the-shelf inductor. For more detailed information on selecting an inductor, please see the "Inductor Selection" section of Linear Technology Application Note 19. Boost Converter: MOSFET Selection The selection criteria of the external N-channel standard level power MOSFET include on resistance (RDS(ON)), reverse transfer capacitance (CRSS), maximum drain source voltage (VDSS), total gate charge (QG) and maximum continuous drain current. For maximum efficiency, minimize RDS(ON) and CRSS. Low RDS(ON) minimizes conduction losses while low CRSS minimizes transition losses. The problem is that RDS(ON) is inversely related to CRSS. Balancing the transition losses with the conduction losses is a good idea in sizing the MOSFET. Select the MOSFET to balance the two losses. Calculate the maximum conduction losses of the MOSFET:
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IOUT(MAX ) PCOND = DCMAX * RDS(ON) 1- DC
MAX
Note that RDS(ON) has large positive temperature dependence. The MOSFET manufacturer's data sheet contains a curve, RDS(ON) vs Temperature. Calculate the maximum transition losses:
PTRAN =
(k )( VOUT )
2
(IOUT(MAX) )(CRSS )( fSW )
(1- DCMAX )
where k is a constant inversely related to the gate driver current, approximated by k = 2 for LT3844 applications. The total maximum power dissipation of the MOSFET is the sum of these two loss terms: PFET(TOTAL) = PCOND + PTRAN To achieve high supply efficiency, keep the PFET(TOTAL) to less than 3% of the total output power. Also, complete a thermal analysis to ensure that the MOSFET junction temperature is not exceeded. TJ = TA + PFET(TOTAL) * JA where JA is the package thermal resistance and TA is the ambient temperature. Keep the calculated TJ below the maximum specified junction temperature, typically 150C. Note that when VOUT is high (>20V), the transition losses may dominate. A MOSFET with higher RDS(ON) and lower CRSS may provide higher efficiency. MOSFETs with higher voltage VDSS specification usually have higher RDS(ON) and lower CRSS. Choose the MOSFET VDSS specification to exceed the maximum voltage across the drain to the source of the MOSFET, which is VOUT plus the forward voltage of the rectifier, typically less than 1V. The internal VCC regulator is capable of sourcing up to 40mA which limits the maximum total MOSFET gate charge, QG, to 40mA / fSW. The QG vs VGS specification is typically provided in the MOSFET data sheet. Use QG at VGS of 8V. If VCC is back driven from an external supply, the MOSFET drive current is not sourced from the internal regulator of the LT3844 and the QG of the MOSFET is not
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limited by the IC. However, note that the MOSFET drive current is supplied by the internal regulator when the external supply back driving VCC is not available such as during startup or short-circuit. The manufacturer's maximum continuous drain current specification should exceed the peak switch current which is the same as the inductor peak current, IL(MAX) + IL/2. During the supply startup, the gate drive levels are set by the VCC voltage regulator, which is approximately 8V. Once the supply is up and running, the VCC can be back driven by an auxiliary supply such as VOUT. It is important not to exceed the manufacturer's maximum VGS specification. A standard level threshold MOSFET typically has a VGS maximum of 20V. Boost Converter: Rectifier Selection The rectifier is selected based upon the forward voltage, reverse voltage and maximum current. A Schottky diode is recommended for its low forward voltage and yields the lowest power loss and highest efficiency. The maximum reverse voltage that the diode will see is VOUT. The average diode current is equal to the maximum output load current, IOUT(MAX). A diode rated at 1.5 to 2 times the maximum average diode current is recommended. Remember boost converters are not short circuit protected. Boost Converter: Output Capacitor Selection In boost mode, the output capacitor requirements are more demanding due to the fact that the current waveform is pulsed instead of continuous as in a buck converter. The choice of component(s) is driven by the acceptable ripple voltage which is affected by the ESR, ESL and bulk capacitance. The total output ripple voltage is:
ESR 1 VOUT = IOUT(MAX ) + fSW * COUT 1- DCMAX
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where the first term is due to the bulk capacitance and the second term due to the ESR. The choice of output capacitor is also driven by the RMS ripple current requirement. The RMS ripple current is:
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IRMS(COUT ) = IOUT(MAX ) * VOUT - VIN(MIN) VIN(MIN)
At lower output voltages (<30V) it may be possible to satisfy both the output ripple voltage and RMS requirements with one or more capacitors of a single type. However, at output voltages above 30V where capacitors with both low ESR and high bulk capacitance are hard to find, the best approach is to use a combination of aluminum electrolytic and ceramic capacitors. The low ESR ceramic capacitor will minimize the ESR while the Aluminum Electrolytic capacitor will supply the required bulk capacitance. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10F to 100F. A low ESR capacitor is recommended though not as critical as with the output capacitor. The RMS input capacitor ripple current for a boost converter is:
IRMS(CIN) = 0 . 3 * VIN(MIN) L * fSW * DCMAX
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Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors. Boost Converter: RSENSE Selection The boost application in the "Typical Applications" section has the location of the current sense resistor in series with the inductor with one side referenced to VIN. This location was chosen for two reasons. Firstly, the circulating current is always monitored so in the case of an output overvoltage or input over current condition the main switch will skip cycles to protect the circuitry. Secondly, the VIN node can be considered low noise since it is heavily filtered and the input current is not pulsed but continuous. In the case where the input voltage exceeds the voltage limits on the LT3844 Sense pins, the sense resistor can be moved to the source of the MOSFET. In both cases the resistor value is the calculated using the same formula. The LT3844 current comparator has a maximum threshold of 100mV/RSENSE. The current comparator threshold sets the peak of the inductor current. Allowing adequate margin for ripple current and external component tolerances, RSENSE can be calculated as follows:
RSENSE = 70mV IL(MAX )
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Where IL(MAX) is the maximum average inductor current as calculated in the "Boost Converter: Inductor Selection" section.
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TYPICAL APPLICATIO S
All Ceramic Capacitor Application, 24V to 3.3V at 5A, fSW = 250kHz
VIN 24V (VOLTAGE TRANSIENTS UP TO 60V) CIN 22F x3 R3 1M C5 0.22F M1
C1 2200pF
R2 5.62k
R1 3.32k
R4 10k C2 680pF
C3 100pF
VIN 12V
CIN1 22F x3 25V
CIN2 1F 25V
R4 1M C1 3300pF
R2 54.9k
R1 10k C2 100pF
R5 40.2k C3 680pF
R3 49.9k
L1 = COILTRONICS, VERSAPAC VP5-0083 CIN, C5, COUT2 = TDK, C4532X7R1E226M D2 = ONSEMI, MBRD660 COUT = SANYO OS-CON, 16SVP330M CIN = VISHAY, Si7852DP
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1 2 3 4 5 6 7 8
VIN
SHDN CSS BURST_EN
BOOST TG SW VCC LT3844 PGND SENSE+
16 15 14 13 12 11
VFB VC SYNC fSET
C4 2.2F
D2
IN4148
L1 6.8H
RSENSE 0.01
VOUT 3.3V AT 5A 100F COUT x2
D1
10 SENSE-
SGND
9
3844 TA02
R5 63.4k
L1 = VISHAY, IHLP5050FD-01 M1 = VISHAY, SI7852DP D1 = DIODES INC, PDS760 COUT = TDK, C4532X5R0J107K CIN = TDK, C4532X7R2A225K
8V to 20V to 8V, 25W SEPIC Application
C5 22F x3 25V
1 2 3 4 5 6
VIN
SHDN CSS BURST_EN
BOOST TG SW VCC LT3844 PGND SENSE+ SENSE- SGND
16 15 14 13 12 11 10 9
*
L1
D2 VOUT 8V AT 25W
M1
VFB VC
C4 1F 25V
R6 10 RSENSE 0.01
+
L1
*
COUT1 330F 16V
COUT2 22F 25V
56pF
7 SYNC 8 fSET
R7 10
3844 TA03
3844fa
21
LT3844
TYPICAL APPLICATIO S
Two Phase Spread Spectrum 24V Input to 12V, 6A Output
C5 0.22F 16V
1 2 16
R3 3M
R6 270k
C1 2200pF
R2 87.5k
VIN 18V TO 36V
R1 10k
R4 4.99k C2 680pF
SYNC1 8
CIN 6.8F x3 50V
R22 10K R21 49.9K
1 2 3 4 SYNC1 10 9
V+
DIV
SET MOD LTC6902 GND OUT2
PH OUT1
8 6 5 SYNC2
C13 47pF
3
1
OUT
VIN
LT1121-5 GND
2
22
U
VIN
SHDN CSS BURST_EN
BOOST
15
TG
14
M1
3 4
SW
13
VCC LT3844
12
5 6
VFB VC
PGND SENSE+ SENSE- SGND
11 10 9
C4 2.2F
L1 15H D1a BAV70 D1 D1b BAV70
RSENSE 0.02 COUT 22F 25V
VOUT 12V AT 6A
7 SYNC fSET
R5 49.9k
R13 3M
C15 0.22F 16V
1 2
VIN
SHDN CSS BURST_EN
BOOST TG SW VCC LT3844 PGND SENSE+ SENSE- SGND
16 15 14 13 12 11 10 9 L1, L11 = VISHAY, IHLP5050FD-01 M1, M11 = VISHAY, Si7850DP D1, D11 = DIODES INC, PDS760 COUT = TDK, C4532X7R1E226K CIN = TDK, C4532X7R1H685K
3844 TA04
R16 270k
C11 2200pF
M11
3 4 5
VFB VC
C14 2.2F
L1 15H D11a BAV70 D11 D11b BAV70
RSENSE 0.02
7 SYNC2 8 SYNC fSET
R12 87.5k
R11 10k
R15 49.9k
3844fa
LT3844
PACKAGE DESCRIPTIO U
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
3.58 (.141) 4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 6.60 0.10 4.50 0.10
SEE NOTE 4
9
2.94 (.116) 0.45 0.05 1.05 0.10 0.65 BSC
6.40 2.94 (.252) (.116) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3844fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3844
TYPICAL APPLICATIO S
12V to 48V 50W Step Up Converter with 400kHz Switching Frequency
RSENSE 0.01 D1 BAV99 VIN 12V 1
+
CIN 33F x2 25V
C1 0.1F 25V C4 4700pF
R2 383k
R1 10k C2 120pF
R6 40k C3 4700pF
RELATED PARTS
PART NUMBER LT1339 LTC1624 LTC1702A LTC1735 LTC1778 LT3010 LT3430/LT3431 LTC3703/LTC3703-5 LT3724 LT3800 DESCRIPTION High Power Synchronous DC/DC Controller Switching Controller Dual 2-Phase Synchronous DC/DC Controller Synchronous Step-Down DC/DC Controller No RSENSE Synchronous DC/DC Controller 50mA, 3V to 80V Linear Regulator Monolithic 3A, 200kHz/500kHz Step-Down Regulator 100V Synchronous Switching Regulator Controllers High Voltage Current Mode Switching Regulator Controllers High Voltage Synchronous Regulator Controller COMMENTS VIN up to 60V, Drivers 10000pF Gate Capacitance, IOUT = <20A Buck, Boost, SEPIC, 3.5V VIN 36V; 8-Lead SO Package 550kHz Operation, No RSENSE, 3V = 24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
U
VIN
BOOST TG SW
16 15 14 L1 6.8H D2 C5 2.2F 25V
R4 4.7M 2 SHDN 3 CSS 4
VOUT 48V AT 50W
13 VCC BURST_EN LT3844 12 5 PGND VFB 6 7 8 VC SYNC fSET SENSE+ SENSE- SGND 11 10 9
M1
+
COUT1 330F
COUT2 220F
R5 33.2k
3844 TA05
M1 = VISHAY, Si7370DP L1 = VISHAY, IHLP5050FD-01 D2 = DIODES INC., PDS560 CIN = SANYO, 25SVP33M COUT1 = SANYO, 63CE220FST COUT2 = TDK, C4532X7R2A225K RSENSE = IRC, LRF2512-01-R010-F
3844fa LT 0707 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2006

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